RTL design engineer
Open Positions : 3
Experience : 0-2 years
Nature of Work : SOC/IP Design
JOB_ID : OneRupeeST_RTL_2021
Work Location : In-house product development
Job Description : The candidate should have good understanding about the system level design and multiprocessing environment. The candidate should have exposure to Verilog or SystemVerilog.
1. Should have strong understanding of synthesizable designs
2. Should understand the RTL tweaks for performance improvement
3. Should be strong enough to develop the FSM controllers to embed the parallelism using chip.
4. Should have exposure on IP development and ASIC design cycle
5. Should have exposure on ASIC and FPGA tool chain.
SOC Prototype engineer
Open Positions : 2
Experience : 2-4 years
Nature of Work : SOC implementation
JOB_ID : OneRupeeST_SOC_2021
Work Location : In-house/client place if required
Job Description : The candidate should have good understanding of the architecture design for million gate SOCs and complex multi FPGA environment. The candidate should have exposure to implementation and test setup.
1. Should have strong understanding of constraints and system level design.
2. Should understand the speed and Power analysis for performance improvement techniques.
3. Should have strong implementation and debug skills.
4. Should have exposure using high density FPGA boards.
5. Should have domain and working knowledge to create design partitioning, floorplanning, powerplanning.
6. Should have exposure on ASIC/FPGA EDA tools