The summer training program with internship batches will commence from 1 June 2021.
The main objective of these training programs is to offer the practical oriented design using the FPGAs.
These programs will be beneficial to third year and final year engineering students to get hands on experience in the area of design using FPGA and VHDL/Verilog.
Following are the few highlights for the summer training programs and Internship.
Audience: Third year and final year engineering students
Basic Prerequisites: Candidates should have basic understanding of digital logic and should have the laptop with the open source tools.
Duration: 110 Hours (Excluding Saturday and Sunday)
Summer Training batches:
Use the batch code to confirm the registration
: 1 June 2021 to 30 June 2021
: Batch code: ST_2021_001
: Timing: 8.30 AM to 1.30 PM
: 1 June 2021 to 26 June 2021
: Batch code: ST_2021_002
: Timing: 2.00 PM to 7.00 PM
How we deliver sessions?
We deliver session using the
- Interactive Presentations
- Exercises using EDA tools
- Assessment tests
Certificate of Participation
The certificate of participation will be issued at the end of the training program.
Investment for the program
Non-refundable course investment of Rs. 13500/- + 18% GST should be paid on or before first day of training program. Course investment should be paid by cheque or demand draft (payable at Pune) in favor of “1 Rupee S T” !
A. Registration charges: Amount of Rs. 1500/- + 18% GST to confirm the participation should be paid by Demand Draft on or before 15 May 2021
B. Second installment: Amount of Rs. 12000/- + 18% GST should be paid on the first day of summer training program.