1 Rupee S T ( Semiconductor Training @ Rs. 1) is initiative of Vaibbhav Taraate. He is Entrepreneur and Mentor at “Semiconductor Training @ Rs.1”.
He holds a BE (Electronics) degree from Shivaji University, Kolhapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL.
He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.
We offer the modular and corporate training programs in the area of FPGA and ASIC design. The training sessions are designed to deliver practical oriented information to the engineers.
The training session includes :
The training programs are delivered using interactive presentations and the high density FPGA boards. The training sessions are designed to cover the specifications to the implementation flow.