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Corporate Programs

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We provide the corporate training in various VLSI domain to corporates. The list of few of the corporate training programs with innovative way of course structure and which has

  1. Video Sessions
  2. Assignments
  3. Test Series
  4. Exercises

These training programs are useful to the engineers to improve their technical strengths and to get awareness about latest trends in the VLSI domain.

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    1. High Speed Digital Design

    1. Audience : Engineers with sound knowledge of digital design and processor architectures
    2. Duration : 40 Hours(8 hours per day)
    3. Contents
        1. Architecture and Micro-architecture design
        2. Performance improvement techniques
        3. Finite State machines
        4. Multiple Clock domains and data integrity
        5. Design for low power
        6. Controller design and optimization

    2. RTL Design Using Verilog

    1. Audience : Engineers with sound knowledge of digital design and processor architectures
    2. Duration : 40 Hours(8 hours per day)
    3. Contents
        1. ASIC and FPGA design flow
        2. Verilog as HDL
        3. Synthesizable and Non-synthesizable constructs
        4. RTL Design Using Verilog
        5. FSM Design using Verilog
        6. Design for multiple clock domains
        7. RTL design tweaks and performance improvement
        8. Design Synthesis and performance improvement
        9. Project work
    4. Training Material
        1. Interactive Presentations
        2. Assignments
        3. Assessment tests
    5. EDA Tools
        1. FPGA EDA Tools from Xilinx, Intel-FPGA
        2. ASIC EDA Tools : Synopsys, Cadence (ASIC EDA tools should be provided by client during corporate training duration)

    3. RTL Design Using VHDL

    1. Audience : Engineers with sound knowledge of digital design and processor architectures
    2. Duration : 24 Hours(8 hours per day)
    3. Contents
        1. ASIC and FPGA design flow
        2. VHDL Basics
        3. Synthesizable and Non-synthesizable constructs
        4. RTL Design Using VHDL
        5. FSM Design using VHDL
        6. Design for multiple clock domains
        7. RTL design tweaks and performance improvement
        8. Design Synthesis and performance improvement
        9. Project work
    4. Training Material
        1. Interactive Presentations
        2. Exercises using EDA tools
        3. Assignments
        4. Assessment tests
    5. EDA Tools
        1. FPGA EDA Tools from Xilinx, Intel-FPGA
        2. ASIC EDA Tools : Synopsys, Cadence (ASIC EDA tools should be provided by client during corporate training duration)

    4. ASIC Synthesis

    1. Audience : Engineers with sound knowledge of Verilog, VHDL
    2. Duration : 24 Hours(8 hours per day)
    3. Contents
        1. Design Synthesis
        2. Design Constraints
        3. Performance improvement techniques
            RTL level
          4. Synthesis Level
        5. ASIC Vs FPGA synthesis
        6. Case Studies
        7. Project work
    4. Training Material
        1. Interactive Presentations
        2. Exercises using EDA tools
        3. Assignments
        4. Assessment tests
    5. EDA Tools
        1. FPGA EDA Tools from Xilinx, Intel-FPGA
        2. ASIC EDA Tools : Synopsys, Cadence (ASIC EDA tools should be provided by client during corporate training duration)

    5. Design And Implementation Using FPGA

    1. Audience : Engineers with sound knowledge of Verilog, VHDL
    2. Duration : 24 Hours(8 hours per day)
    3. Contents
        1. ASIC and FPGA design flow
        2. HDL constructs
        3. FPGA Architecture
        4. Design for the target FPGA
        5. Design Synthesis and Implementation
        6. Board Bring up and Testing
        7. Project work
    4. Training Material
        1. Interactive Presentations
        2. Exercises using EDA tools
        3. Assignments
        4. Assessment tests
    5. EDA Tools
        1. FPGA EDA Tools from Xilinx, Intel- FPGA